The present invention relates to small geometry MOS semiconductor devices.
A variety of methods and structures have been used to isolate areas on semiconductor devices. One widely used isolation technique is shallow trench isolation (STI), shown in FIG. 5. The field oxide 16 in the silicon substrate 2, is continuous with a surface oxide layer 10. FIGS. 1-4 illustrate the steps used to prepare the structure shown in FIG. 5. Thermal oxidizing forms an oxide layer 10 on the silicon substrate 2, followed by depositing a silicon nitride layer 6 using low pressure chemical vapor deposition (LPCVD), to form the structure shown in FIG. 1. Next, a photoresist layer 4 is applied, and patterned using a mask. Etching of those portions of the silicon nitride, surface oxide layer and silicon substrate not covered by the photoresist layer, in a single operation, opens a trench 8, as shown in FIG. 2.
Then, the photoresist layer 4 is stripped, and the substrate is cleaned. A thin oxide layer 14 is next grown by oxidation of the exposed portions of the silicon substrate. An oxide layer 12 is then deposited into the trench and across the surface of the structure by chemical vapor deposition (CVD), to form the structure shown in FIG. 3. Chemical-mechanical polishing (CMP) is used to planarize the surface, leaving the oxide layer 12 only in the trench, as illustrated in FIG. 4. Finally, the silicon nitride layer is removed, to form the field oxide 16, shown in FIG. 5.
Once the isolation region has been formed, further device fabrication may take place. As shown in FIG. 6, typically the oxide layer 10 is removed, and regrown as a gate layer 11 of an oxide or another insulator, and a gate layer 30 of a conductor, such as polysilicon, is formed and patterned, creating gates over the active regions 36 of the structure. Formide an oxide on the surface of the gate layer, by dry oxidation using oxygen, then seals the gate layer. Further structures to complete the semiconductor devices may be formed from this structure; for example, forming source/drain regions in the substrate may be used to make transistors; these may be connected together through applied dielectric layers by contacts and metallization layers. These additional elements may be formed before, during, or after formation of the isolation regions and the gate layer. FIG. 7 illustrates a top view of FIG. 6, which includes contacts 38 to the active areas 36 of the substrate. The gate length 32 and channel width 34 are also shown in the FIG. 7; the gate length is the distance across the channel, under the gate layer that spans along the length of the active region, and the channel width is the distance between isolation regions.
A disadvantage of the STI technique is the inverse narrow width effect (INWE) that manifests itself as a reduction of the threshold voltage of the transistors as the transistor width decreases. Typically, INWE is significant once the width of the transistor is less than 0.25 xcexcm. This effect has been eliminated or reduced by a variety of different approaches, for example, by adding implants into the sidewalls of the trench; adding extra implants into the channel region of the memory array transistors (a core implant); or adding an additional oxidation step to form a bird""s beak structure at the edges of the active area. These methods all have the disadvantage of requiring additional process steps, increasing the cost and complexity of the process.
In a first aspect, the present invention is a method of making a semiconductor structure, comprising sealing a gate layer by wet oxidation. The gate layer is on a substrate comprising isolation regions.
In a second aspect, the present invention is a method of making a semiconductor structure, comprising simultaneously sealing a gate layer and forming a bird""s beak structure at the interface of the gate layer and isolation regions. The gate layer is on a substrate comprising the isolation regions.
In a third aspect, the present invention is a method of eliminating inverse narrow width effects in a semiconductor device, comprising forming a bird""s beak structure at the interface of a gate layer and isolation regions, by wet oxidation.
In a fourth aspect, the present invention is a method of making a semiconductor device, comprising making any of these semiconductor structures and forming a semiconductor device from the structures.
In a fifth aspect, the present invention is a method of making a semiconductor device, comprising forming isolation regions in a substrate, to form a structure and forming a semiconductor device from the structure. The forming of the semiconductor device does not comprise: adding implants into sidewalls of the isolation regions; adding core implants; nor adding an additional oxidation step to form a bird""s beak structure at the edges of active areas. Furthermore, the semiconductor device does not exhibit inverse narrow width effects, and the semiconductor device comprises transistors having a channel width of at most 0.18 xcexcm.